buffer register

英 [ˈbʌfə(r) ˈredʒɪstə(r)]

美 [ˈbʌfər ˈredʒɪstər]

缓冲寄存器

Print line buffer address register
打印行缓冲地址寄存器
Memory buffer address register
存储器缓冲地址寄存器
There are three main phases: the priorities level management and distributed multi-level buffer of realtime data, multimedia data capture management based on register/ logout model of flexible system, and information syncretization based on multi-thread.
全文探讨了3个主要的问题：实时数据的优先级管理及分布式多级缓冲、基于注册/注销管理模式的数据采集管理与柔性系统设计思想以及基于多线程的信息融合。
The MAC layer controller hardware modules are designed using Verilog hardware description language, including the transmission of the engines, receiving engines, buffer module, register module, control module and the WEP module.
采用Verilog硬件描述语言实现了MAC层控制器的硬件部分，包括发送引擎、接收引擎、缓冲区模块、寄存器模块、控制模块等模块。
The voltage detector includes several sub-systems such as a multi-path selector, a buffer amplifier, a comparator, a 12-bit SAR ADC, a shift register and a status bar.
该电压检测器主要包括多路选通器、缓冲放大器、比较器、12位逐次逼近数模转换器、移位寄存器、状态机等部分。